Cypress Clock CY25822 2 User Manual

CY25822-2  
CK-SSC Spread Spectrum Clock Generator  
Features  
• 3.3V operation  
• 48- and 66-MHz frequency support  
• Selectable slew rate control  
• 350-pS jitter  
2
• I C programmability  
• 500-µA power-down current  
• SpreadSpectrumforbestelectromagneticinterference  
(EMI) reduction  
• 8-pin SOIC package  
Block Diagram  
VDD  
REFOUT  
CLKOUT  
Clock Input  
Freq.  
Divider  
M
Phase  
Detector  
Charge  
Pump  
Post  
Dividers  
(SSCG Output)  
Σ
VCO  
Modulating  
Waveform  
SDATA  
Logic  
Control  
SCLOCK  
Feedback  
Divider  
PWRDWN#  
N
PLL  
GND  
Pin Configuration  
1
2
3
4
8
7
6
5
C LK IN  
*P W R D W N #  
SC LO C K  
SD A TA  
V D D  
G N D  
C Y 25822-2  
C LK O U T  
R E FO U T  
* 150K P ull-up  
Cypress Semiconductor Corporation  
Document #: 38-07531 Rev. **  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised March 18, 2003  
 
CY25822-2  
Table 2. Block Read and Block Write Protocol (continued)  
....  
....  
....  
Data Byte N –8 bits  
Acknowledge from slave  
Stop  
56  
....  
....  
....  
....  
Acknowledge  
Data bytes from slave/Acknowledge  
Data byte N from slave – 8 bits  
Not Acknowledge  
Stop  
Table 3. Byte Read and Byte Write Protocol  
Byte Write Protocol  
Byte Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write = 0  
2:8  
9
Slave address – 7 bits  
Write = 0  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
11:18  
Command Code – 8 bits  
'1xxxxxxx' stands for byte operation, bits[6:0] of  
the command code represents the offset of the  
byte to be accessed  
'1xxxxxxx' stands for byte operation, bits[6:0]  
of the command code represents the offset of  
the byte to be accessed  
19  
20:27  
28  
Acknowledge from slave  
Data byte from master – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
Acknowledge from slave  
Repeat start  
21:27  
28  
Slave address – 7 bits  
Read = 1  
29  
29  
Acknowledge from slave  
Data byte from slave – 8 bits  
Not Acknowledge  
Stop  
30:37  
38  
39  
Byte 0: Control Register  
Bit  
7
@Pup  
Pin#  
Name  
Pin Description  
1
0
0
0
1
1
4
4
4
4
SS0  
SS1  
SS2  
SS3  
6
5
4
3
Not Applicable  
Reserved, must be written as 1  
2
4, 5 CLKOUT,  
REFOUT  
Power-down three-state enable  
0 = three-state outputs, 1 = drive outputs low  
(Applies only in Power Down State)  
1
0
1
0
4
CLKOUT  
Spread Spectrum enable  
0 = spread off, 1 = spread on  
Not Applicable  
No Pins  
Table 4. Spread Spectrum Select  
SS3  
0
SS2  
0
SS1  
0
SS0  
0
Spread Mode  
Down  
Spread Amount%  
0.8  
1.0  
0
0
0
1
Down  
0
0
1
0
Down  
1.25  
1.5  
0
0
1
1
Down  
0
1
0
0
Down  
1.75  
Document #: 38-07531 Rev. **  
Page 3 of 9  
 
CY25822-2  
Table 4. Spread Spectrum Select (continued)  
SS3  
0
SS2  
1
SS1  
0
SS0  
1
Spread Mode  
Down  
Spread Amount%  
2.0  
2.5  
0
1
1
0
Down  
0
1
1
1
Down  
3.0  
1
0
0
0
Center  
Center  
Center  
Center  
Center  
Center  
Center  
Center  
±0.3  
±0.4  
±0.5  
±0.6  
±0.8  
±1.0  
±1.25  
±1.5  
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Byte 1: Control Register  
Bit  
@Pup  
Pin#  
Name  
Pin Description  
7
1
5
REFEN  
REFSLEW  
REFOUT enable  
0 = disabled, 1 = enabled  
6
1
5
REFOUT edge rate control  
0 = slow, 1 = nominal  
5
4
3
0
0
1
Not Applicable  
Not Applicable  
CLKSLEW  
Reserved.  
Reserved  
4
4
CLKOUT edge rate control  
0 = slow, 1 = nominal  
2
1
CLKEN  
CLKOUT enable  
0 =disabled, 1 = enabled  
1
0
0
0
Not Applicable  
Not Applicable  
Reserved  
Reserved  
Bytes 2 through 5: Reserved Registers  
PWRDWN# (Power-down) Clarification  
The PWRDWN# (Power-down) pin is used to shut off ALL  
clocks prior to shutting off power to the device. PWRDWN# is  
an asynchronous active LOW input. This signal is synchro-  
nized internally to the device powering down the clock synthe-  
sizer. PWRDWN# is an asynchronous function for powering up  
the system. When PWRDWN# is low, all clocks are driven to  
a LOW value and held there and the VCO and PLLs are also  
powered down. All clocks are shut down in a synchronous  
manner so has not to cause glitches while transitioning to the  
low ‘stopped’ state. When PWRDWN# is deasserted the  
clocks should remain stopped until the VCO is stable and  
Byte 6: Vendor/Revision ID Register  
Bit @Pup  
Pin#  
Name  
Pin Description  
Revision ID Bit 3  
Revision ID Bit 2  
Revision ID Bit 1  
Revision ID Bit 0  
Vendor ID Bit 3  
Vendor ID Bit 2  
Vendor ID Bit 1  
Vendor ID Bit 0  
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
within specification (t  
). A stopped clock is either  
STABLE  
tri-stated or driven low depending on the state of the tri-state  
2
enable I C register bit. CY25822 clocks that are stopped in the  
driven state are driven low.  
The CLKIN input must be on and within specified operating  
parameters before PWRDWN# is asserted and it must remain  
in this state while PWRDWN# is asserted.  
Document #: 38-07531 Rev. **  
Page 4 of 9  
 
CY25822-2  
PWRDWN#  
CLKOUT  
REFOUT  
Figure 1. Power-down Assertion  
PD#  
CLKOUT  
REFOUT  
<3.0ms  
Figure 2. Power-down Deassertion  
CLKOUT and REFOUT Enable Clarification  
2
The CLKOUT enable and REFOUT enable I C register bits are  
used to shot-off the CLKOUT and REFOUT clocks individually.  
The VCO and crystal oscillator must remain on. A shutdown  
clock is driven low. ALL clocks need to be stopped in a  
predictable manner. All clocks need to be shutdown without  
any glitches or other abnormal behavior while transitioning to  
a stopped state. Similarly when CLKOUT or REFOUT is  
enabled the clock must start in a predictable manner without  
any glitches or abnormal behavior.  
Document #: 38-07531 Rev. **  
Page 5 of 9  
 
CY25822-2  
Table 5. Absolute Maximum Ratings  
Parameter Description  
Core Supply Voltage  
Condition  
Min.  
–0.5  
–0.5  
–0.5  
–65  
0
Max.  
Unit  
V
V
4.6  
4.6  
DD  
DD_A  
IN  
V
V
Analog Supply Voltage  
Input Voltage  
V
Relative to V  
V
+ 0.5  
DD  
VDC  
°C  
SS  
T
Temperature, Storage  
Temperature, Operating Ambient  
Temperature, Junction  
Non Functional  
+150  
70  
S
T
Functional  
Functional  
°C  
A
T
150  
°C  
J
ESD  
ESD Protection (Human Body Model) MIL-STD-883, Method 3015  
2000  
Volts  
HBM  
UL–94  
MSL  
Flammability Rating  
@1/8 in.  
V–0  
Moisture Sensitivity Level  
1
Table 6. DC Parameters (T = 0°C to +70°C, V = 3.3V ± 5%)  
A
DD  
Parameter  
Description  
Condition  
Min.  
3.135  
2.0  
Max  
Unit  
V
Notes  
= 3.3 ± 5%  
V
Supply Voltage  
3.465  
V
DD  
DD  
IH  
IL  
V
V
Input High Voltage  
Input Low Voltage  
V
+ 0.3  
V
DD  
V
– 0.3  
0.8  
V
SS  
I
Input Leakage Current  
SCLOCK  
or SDATA  
–25  
+25  
µA  
IL1  
I
Input Leakage Current  
Output High Voltage  
PWRDWN#  
–75  
2.4  
–15  
µA  
IL2  
V
I
= –4 mA  
V
Single edge is required to  
be monotonic when transi-  
tioning through this region.  
OH  
OH  
V
Output Low Voltage  
I
= 4 mA  
0.4  
V
Single edge is required to  
be monotonic when transi-  
tioning through this region.  
OL  
OL  
C
C
Input Pin Capacitance  
Output Pin Capacitance  
Pin Inductance  
0
5
6
pF  
pF  
nH  
IN  
OUT  
IN  
L
7
T
Ambient Temperature  
Supply Current  
70  
50  
40  
500  
°C No air flow  
A
I
I
I
@ 66 MHz  
@ 48 MHz  
mA  
mA  
µA  
DD1  
DD2  
PD  
Supply Current  
Power Down Supply Current  
Table 7. AC Parameters (T = 0°C to +70°C, V = 3.3V ± 5%)  
A
DD  
Parameter  
Description  
Conditions  
Measured @2.4V  
Min.  
Max.  
Unit  
Notes  
t
CLK High Time, 48MHz  
9.45  
10.95  
10.10  
7.90  
6.95  
5.0  
ns Specification applies to  
48MHz output mode.  
HIGH  
t
CLK, Low Time, 48MHz Measured @0.4V  
8.50  
6.85  
5.95  
2.0  
ns Specification applies to  
48MHz output mode.  
LOW  
HIGH  
t
CLK High Time, 66MHz  
CLK Low Time, 66MHz  
Rising Edge Rate  
Measured @2.4V  
Measured @0.4V  
ns Specification applies to  
66.7MHz output mode.  
t
ns Specification applies to  
66.7MHz output mode.  
LOW  
t
t
Measured from 0.4V to 2.4V  
REFOUT and CLOCKOUT  
V/ns High Buffer Strength  
RISEH1  
FALLH1  
2
Refer to I C Control  
Falling Edge Rate  
Measured from 2.4V to 0.4V  
REFOUT and CLOCKOUT  
2.0  
5.0  
V/ns High Buffer Strength  
2
Refer to I C Control  
t
Rising Edge Rate  
Measured from 0.4V to 2.4V  
REFOUT and CLOCKOUT  
1.33  
4.0  
V/ns Low Buffer Strength  
RISEL1  
2
Refer to I C Control  
Document #: 38-07531 Rev. **  
Page 6 of 9  
 
CY25822-2  
Table 7. AC Parameters (T = 0°C to +70°C, V = 3.3V ± 5%) (continued)  
A
DD  
Parameter  
Description  
Conditions  
Min.  
Max.  
Unit  
Notes  
t
Falling Edge Rate  
Measured from 2.4V to 0.4V  
REFOUT and CLOCKOUT  
1.33  
4.0  
V/ns Low Buffer Strength  
FALLL1  
RISEH2  
FALLH2  
2
Refer to I C Control  
t
t
Rise Time  
Fall Time  
Rise Time  
Fall Time  
Measured from 0.4V to 2.4V  
REFOUT and CLOCKOUT  
0.4  
0.4  
0.5  
0.5  
1.0  
1.0  
1.5  
1.5  
ns High Buffer Strength  
2
Refer to I C Control  
Measured from 2.4V to 0.4V  
REFOUT and CLOCKOUT  
ns High Buffer Strength  
2
Refer to I C Control  
t
t
Measured from 0.4V to 2.4V  
REFOUT and CLOCKOUT  
ns Low Buffer Strength  
RISEL2  
FALLL2  
2
Refer to I C Control  
Measured from 2.4V to 0.4V  
REFOUT and CLOCKOUT  
ns Low Buffer Strength  
2
Refer to I C Control  
T
T
Cycle to Cycle Jitter  
Cycle to Cycle Jitter  
10µS Period Jitter  
REFOUT  
500  
250  
2.0  
ps SSCG is ON  
ps SSCG is ON  
CYC1  
CLOCKOUT  
CYC2  
LTJ  
Applies to REFOUT at all  
ns  
(100KHz, Frequency Mod- timesandCLOCKOUTwhen  
ulation Amplitude)  
SSCG is Off  
t
Start up time  
From VDD = 2.0 V  
3.0  
ms All outputs disabled  
START  
Table 8. Signal Loading Table  
Clock Name  
Max Load (pF)  
15  
CLKOUT, REFOUT  
Ordering Information  
Part Number  
CY25822SC–2  
Package Type  
Product Flow  
8-pin SOIC  
8-pin SOIC – Tape and Reel  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
CY25822SC–2T  
Document #: 38-07531 Rev. **  
Page 7 of 9  
 
CY25822-2  
Package Diagram  
8-lead (150-Mil) SOIC – S8  
51-85066-*B  
2
Purchase of I C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips  
2
2
2
I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification  
as defined by Philips.All product and company names mentioned in this document are trademarks of their respective holders.  
Document #: 38-07531 Rev. **  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
 
CY25822-2  
Document History Page  
Document Title: CY25822-2 CK-SSC Spread Spectrum Clock Generator  
Document Number: 38-07531  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
124462  
03/19/03  
RGL  
New Data Sheet  
Document #: 38-07531 Rev. **  
Page 9 of 9  
 

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